preliminary cy2xp21 125 mhz lvpecl clock generator cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-52849 rev. *a revised june 15, 2009 features one lvpecl output pair output frequency: 112 mhz to 140 mhz external crystal frequency: 22.4 mhz to 28 mhz low rms phase jitter at 125 mhz, using 25 mhz crystal (1.875 mhz to 20 mhz): 0.4 ps (typical) pb-free 8-pin tssop package supply voltage: 3.3v or 2.5v commercial and industrial temperature ranges functional description the cy2xp21 is a pll (phase locked loop) based high performance clock generator. it is optimized to generate a 125 mhz clock, which is ideal fo r 10 gb ethernet applications. it also produces an output frequency that is five times the crystal frequency. it uses cypress?s low noise vco technology to achieve less than 1 ps typical rms phase jitter. the cy2xp21 has a crystal oscillator interface input and one lvpecl output pair. output divider crystal oscillator clk# lo w -n ois e pll clk xout xin external crystal logic block diagram pinouts figure 1. pin diagram - 8-pin tssop 1 2 36 7 8 xout xin nc vss vdd clk# 45 vdd clk table 1. pin definition - 8-pin tssop pin number pin name i/o type description 1, 8 vdd power 3.3v or 2.5v power supply 2 vss power ground 3, 4 xout, xin xtal output and input parallel resonant crystal interface 5 nc no connect 6,7 clk#, clk lvpecl output di fferential clock output [+] feedback [+] feedback
preliminary cy2xp21 document #: 001-52849 rev. *a page 2 of 7 frequency table inputs output frequency (mhz) crystal frequency (mhz) pll multiplier value 25 5 125 26.6 5 133 absolute maximum conditions parameter description conditions min max unit v dd supply voltage ?0.5 4.4 v v in [1] input voltage, dc relative to v ss ?0.5 v dd + 0.5 v t s temperature, storage non operating ?65 150 c t j temperature, junction 135 c esd hbm esd protection, human body model jedec std 22-a114-b 2000 v ul?94 flammability rating at 1/8 in. v?0 ja [2] thermal resistance, junction to ambient 0 m/s airflow 100 c/w 1 m/s airflow 91 2.5 m/s airflow 87 notes 1. the voltage on any input or io pin cannot exceed the power pin during power up. 2. simulated using apache sentinel ti software. the board is deri ved from the jedec multilayer standard. it measures 76 x 114 x 1.6 mm and has 4-layers of copper (2/1/1/2 oz.). the internal layers are 100% copper pla nes, while the top and bottom layers have 50% metalization. no via s are included in the model. 3. i dd includes approximately 24 ma of current that is dissi pated externally in the output termination resistors. operating conditions parameter description min max unit v dd 3.3v supply voltage 3.135 3.465 v 2.5v supply voltage 2.375 2.625 v t a ambient temperature, commercial 0 70 c ambient temperature, industrial ?40 85 c t pu power up time for all v dd to reach minimum specified voltage (ensure power ramps is monotonic) 0.05 500 ms dc electrical characteristics parameter description test conditions min typ max unit i dd [4] operating supply current with output terminated v dd = 3.465v, output terminated ? ? 150 ma v dd = 2.625v, output terminated ? ? 145 ma v oh lvpecl output high voltage v dd = 3.3v or 2.5v, r term = 50 to v dd ? 2.0v v dd ?1.15 ? v dd ?0.75 v v ol lvpecl output low voltage v dd = 3.3v or 2.5v, r term = 50 to v dd ? 2.0v v dd ?2.0 ? v dd ?1.625 v v od1 lvpecl peak-to-peak output voltage swing v dd = 3.3v or 2.5v, r term = 50 to v dd ? 2.0v 600 ? 1000 mv v od2 lvpecl output voltage swing (v oh - v ol ) v dd = 2.5v, r term = 50 to v dd ? 1.5v 500 ? 1000 mv v ocm lvpecl output common mode voltage (v oh + v ol )/2 v dd = 2.5v, r term = 50 to v dd ? 1.5v 1.2 ? ? v c inx pin capacitance, xin & xout 4.5 pf [+] feedback [+] feedback
preliminary cy2xp21 document #: 001-52849 rev. *a page 3 of 7 parameter measurements figure 2. 3.3v output load ac test circuit figure 3. 2.5v output load ac test circuit ac electrical characteristics [4] parameter description conditions min typ max unit f out output frequency 112 ? 140 mhz t r , t f output rise or fall time 20% to 80% of full output swing ? 500 ? ps t jitter( ) rms phase jitter (random) 125 mhz, (1.875?20 mhz) ? 0.4 ? ps t dc output duty cycle measured at zero crossing point 48 ? 52 % t lock startup time time for clk to reach valid frequency measured from the time v dd = v dd (min.) ??10ms recommended crystal specifications [5] parameter description min max unit mode mode of oscillation fundamental f frequency 22.4 28 mhz esr equivalent series resistance ? 50 c 0 shunt capacitance ? 7 pf notes 4. inot 100% tested, guaranteed by design and characterization. 5. characterized using an 18 pf parallel resonant crystal. scope v dd v ss lvpecl 50 50 z = 50 z = 50 clk# clk 2v -1.3v +/- 0.165v scope v dd v ss lvpecl 50 50 z = 50 z = 50 clk# clk 2v -0.5v +/- 0.125v [+] feedback [+] feedback
preliminary cy2xp21 document #: 001-52849 rev. *a page 4 of 7 figure 4. output dc parameters figure 5. output rise and fall time figure 6. rms phase jitter figure 7. output duty cycle clk v a v b clk# v od v ocm = (v a + v b )/2 20% 80% t r clk 20% 80% clk# t f phase noise phase noise mask offset frequency f1 f2 rms jitter = area under the masked phase noise plot noise power clk t pw t period t dc = t pw t period clk# [+] feedback [+] feedback
preliminary cy2xp21 document #: 001-52849 rev. *a page 5 of 7 application information power supply filtering techniques as in any high speed analog circuitry, noise at the power supply pins can degrade performance. to achieve optimum jitter perfor- mance, use good power supply isolation practices. figure 8 illus- trates a typical filtering schem e. since all the current flows through pin 1, the resistance and inductance between this pin and the supply is minimized. a 0.01 or 0.1 f ceramic chip capacitor is also located close to this pin to provide a short and low impedance ac path to ground. a 1 to 10 f ceramic or tantalum capacitor is located in the general vicinity of this device and may be shared with other devices. figure 8. power supply filtering termination for lvpecl output the cy2xp21 implements its lvpecl driver with a current steering design. for proper opera tion, it requires a 50 ohm dc termination on each of the two output signals. for 3.3v operation, this data sheet specif ies output levels for termination to v dd ?2.0v. this same termination voltage can also be used for v dd = 2.5v operation, or it can be terminated to v dd -1.5v. note that it is also possible to terminate with 50 ohms to ground (v ss ), but the high and low signal levels differ from the data sheet values. termination resistors are best located close to the desti- nation device. to avoid reflections, trace characteristic impedance (z 0 ) should match the termination impedance. figure 9 shows a standard termination scheme. figure 9. lvpecl output termination crystal interface the cy2xp21 is characterized with 18 pf parallel resonant crystals. the capacitor values shown in figure 10 are deter- mined using a 25 mhz 18 pf parallel resonant crystal and are chosen to minimize the ppm error. note that the optimal values for c1 and c2 depend on the parasitic trace capacitance and are thus layout dependent. figure 10. crystal input interface board layout and nc pin pin 5 (nc) does not perform any function on the cy2xp21. although not used electrically, it is very useful for heat dissi- pation. for this reason, users are advised to connect pin 5 to either a v dd or v ss plane. this helps to lower the thermal resis- tance of the board / package combination, thus reducing the die temperature. 3.3v 10 f 0.1 f v dd v dd 0.01 f (pin 1) (pin 8) clk 84 84 z0 = 50 z0 = 50 3.3v 125 125 in clk# device xin xout x1 18 pf parallel crystal c1 30 pf c2 27 pf [+] feedback [+] feedback
preliminary cy2xp21 document #: 001-52849 rev. *a page 6 of 7 package drawing and dimensions figure 11. 8-pin thin shrunk small outline package (4.40 mm body) z8 ordering information part number package type product flow cy2xp21zxc 8-pin tssop commercial, 0c to 70c CY2XP21ZXCT 8-pin tssop - tape and reel commercial, 0c to 70c cy2xp21zxi 8-pin tssop industrial, -40c to 85c cy2xp21zxit 8-pin tssop - tape and reel industrial, -40c to 85c 8 pin1id seating plane 1 bsc. bsc 0-8 plane gauge 2.90[0.114] 1.10[0.043] max. 0.65[0.025] 0.20[0.008] 0.05[0.002] 6.50[0.256] 0.076[0.003] 6.25[0.246] 4.50[0.177] 4.30[0.169] 3.10[0.122] 0.15[0.006] 0.19[0.007] 0.30[0.012] 0.09[[0.003] 0.25[0.010] 0.70[0.027] 0.50[0.020] 0.95[0.037] 0.85[0.033] dimensions in mm[inches] min. max. 51-85093-a [+] feedback [+] feedback
document #: 001-52849 rev. *a revised june 15, 2009 page 7 of 7 all products and company names mentioned in this document may be the trademarks of their respective holders. preliminary cy2xp21 ? cypress semiconductor corporation, 2009. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rig hts. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with cypres s. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a ma lfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and international treaty provisions . cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution cente rs, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products psoc psoc.cypress.com clocks & buffers clocks.cypress.com wireless wireless.cypress.com memories memory.cypress.com image sensors image.cypress.com psoc solutions general psoc.cypress.com/solutions low power/low voltage psoc.cypress.com/low-power precision analog psoc.cypress.com/precision-analog lcd drive psoc.cypress.com/lcd-drive can 2.0b psoc.cypress.com/can usb psoc.cypress.com/usb document history page document title: cy2xp21 12 5 mhz lvpecl clock generator document number: 001-52849 rev. ecn no. submission date orig. of change description of change ** 2700242 04/30/2009 kvm/pyrs new data sheet *a 2718898 06/15/09 wwz minor ecn to post data sheet to external web [+] feedback [+] feedback
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